1. Field of the Invention
This invention relates generally to memory systems, and more particularly to a semiconductor memory organized into several segments.
2. Description of the Prior Art
Advancements in manufacturing equipment and know-how has reduced considerably the manufacturing costs of integrated circuit semiconductor chips. However, each new generation of random access memories (RAMs), due to their greater complexity and density, requires substantial increases in test times.
A memory comprised of N.times.1 bits is capable of storing as many as 2.sup.N different data patterns. It would not be practical to use 2.sup.N data patterns to test the memory; however, judicious application of product knowledge and test experience will result in the development of a short but effective test method.
A simple pattern (e.g. a checkerboard pattern) requires a minimum test time of 2N cycles, N cycles for writing and N cycles for reading. However, simple data patterns (e.g. checkerboard, solid ones, solid zeros) may not effectively test the memory.
With the increase in memory chip density and decrease in memory cell size and the corresponding reduction in margins, it has become increasingly important that a memory bit be tested not only under the influence of nearby bits but also under the influence of data patterns in other memory segments. Generally, test time (t) is defined by: EQU t=KN.sup.x ( 1)
where K is a constant, N is the memory density and x is a positive number greater than one. Thus, the test time associated with dynamic RAMs increases far more rapidly than does their density. As a result, the costs associated with the testing of semiconductor memories now represents a significant portion of the total manufacturing cost.
One method of reducing test cost involves organizing the memory chip with multiple input and output pins so as to permit simultaneous testing of several sections of the memory. This, however, increases pin count which increases the cost of the package and associated assembly cost and reduces memory board density, increasing overall memory system cost.